Union Semiconductor (Hefei) Co (SHSE:688403) Current Deferred Revenue : ¥0 Mil (As of Mar. 2024)

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What is Union Semiconductor (Hefei) Co Current Deferred Revenue?

Current Deferred Revenue represents collections of cash or other assets related to revenue producing activity for which revenue has not yet been recognized. Generally, an entity records deferred revenue when it receives consideration from a customer before achieving certain criteria that must be met for revenue to be recognized in conformity with GAAP. It can be either current or non-current item. Also called unearned revenue.

Union Semiconductor (Hefei) Co's current deferred revenue for the quarter that ended in Mar. 2024 was ¥0 Mil.

Union Semiconductor (Hefei) Co Current Deferred Revenue Historical Data

The historical data trend for Union Semiconductor (Hefei) Co's Current Deferred Revenue can be seen below:

* For Operating Data section: All numbers are indicated by the unit behind each term and all currency related amount are in USD.
* For other sections: All numbers are in millions except for per share data, ratio, and percentage. All currency related amount are indicated in the company's associated stock exchange currency.

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Union Semiconductor (Hefei) Co Current Deferred Revenue Chart

Union Semiconductor (Hefei) Co Annual Data

Trend

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Current Deferred Revenue

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Union Semiconductor (Hefei) Co Quarterly Data
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Union Semiconductor (Hefei) Co (SHSE:688403) Business Description

Industry

GURUFOCUS.COM » STOCK LIST » Technology » Semiconductors » Union Semiconductor (Hefei) Co Ltd (SHSE:688403) » Definitions » Current Deferred Revenue

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Traded in Other Exchanges

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Address

Hefei Comprehensive Bonded Zone, Xinzhan District, Anhui Province, Hefei, CHN, 230012

Website

http://www.unionsemicon.com.cn

Union Semiconductor (Hefei) Co Ltd is a high-end advanced packaging and testing service provider for integrated circuits. It focuses on the field of display driver chips. The company's main business is the front-end gold bumping manufacturing as the core and integrates wafer testing, back-end chip-on-glass, and chip-on-film links to form a full range of display driver chips.

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