- Cadence (CDNS, Financial) introduces the industry's first DDR5 12.8Gbps MRDIMM Gen2 memory IP solution.
- The new solution doubles the bandwidth of current DDR5 6400Mbps DRAM parts.
- The memory IP system is validated in hardware and is designed for enterprise and data center AI applications.
Cadence Design Systems, Inc. (CDNS) has announced a groundbreaking development in memory technology with the introduction of the industry's first DDR5 12.8Gbps MRDIMM Gen2 memory IP system solution. This innovative system is built on TSMC's advanced N3 process and is specifically designed to meet the demanding AI processing needs of enterprise and data center applications.
The new DDR5 MRDIMM IP system offers a significant advancement by doubling the bandwidth compared to the existing DDR5 6400Mbps DRAM modules. This enhancement is achieved through a complete memory subsystem that integrates both a PHY and a high-performance controller, validated in hardware with the latest Gen2 MRDIMMs.
The solution's compatibility with Micron's 1?-based DRAM and Montage Technology's MRCD02/MDB02 chips ensures a robust ecosystem, ready to support next-generation server and data center products. The IP system is designed to facilitate advanced SoCs and chiplets, offering flexible floorplan options while maintaining ultra-low latency encryption and advanced RAS features—essential for ensuring reliability in high-performance computing environments.
Cadence's collaboration with industry leaders such as Micron and Montage underscores the solution's readiness for market adoption, with several customer engagements already secured. This strategic positioning strengthens Cadence’s footprint in the rapidly expanding AI infrastructure sector, addressing key bottlenecks in system architecture for AI-intensive workloads.
As Boyd Phelps, Senior Vice President at Cadence, noted, the introduction of this cutting-edge memory IP system not only sets a new performance benchmark but also establishes a roadmap for future-proofing customer investments in next-generation SoC and chiplet products. For further details, interested parties are encouraged to visit Cadence’s official page on the DDR5 MRDIMM PHY and controller.
