TSMC (TSM.US) is finalizing specifications for a new "panel-level packaging" technology using square substrates. This development targets high-performance artificial intelligence (AI) chips and aims to begin small-scale production by 2027.
Traditionally, most chips are manufactured on 300mm diameter circular wafers. TSMC's new approach, however, employs a square substrate that accommodates more chip components, enhancing computational efficiency. The first generation of TSMC's panel-level packaging will utilize a 310mm x 310mm square substrate, smaller than the previously tested 510mm x 515mm but larger in effective area than conventional circular wafers.
TSMC plans to stringently control quality and has opted to start with the smaller square dimension to ensure precision and reliability in production.
